Jobs in Rambus Bangalore- Principal Engineer - Design Solutions

Role: Database Architect/Designer
Industry Type: Semiconductors, Electronics
Functional Area: Embedded/EDA /VLSI/ASIC/Chip Design
Designation:  Principal Engineer - Design Solutions
Experience:  8 - 10 Years
Education:  UG - B.Tech/B.E. - Computers, Electrical, B.Sc - Computers
PG - M.Tech - Electrical, Computers, M.Sc - Computers
Location:  Bengaluru/Bangalore


Job Description:-
Work as part of the Design Solutions team to be the lead engineer in implementing Rambus testchips and lead soft macro block implementations using state of the art mixed-signal & digital design flows. Primary responsibility to interface with other Rambus teams to integrate IP into a testchip platform, and implement the design using ASIC methodologies including synthesis, place and route, static timing analysis, and physical verification. Responsibilities include all tapeout related activities. The candidate must have hands-on experience with ASIC design tools in 40 or 28 nm process technologies. The candidate should demonstrate leadership in design techniques related to ASIC design integration of mixed-signal designs.

Profile Requirements:-
• B.S. or M.S. in Electrical Engineering or Computer Science with at least 8 to 10 years of experience in ASIC implementation
• Hands on experience using tools for: RTL creation, Synthesis, Auto Placement and Routing, DFT Scan implementation, Static Timing Analysis, Logic Equivalence Checking, DRC, LVS, DFM, parasitic extraction
• Specifically Digital P&R implementation tools, PrimeTime-SI, Conformal, Calibre, Star-RCXT.
• Knowledge of functional verification a plus
• Working knowledge of shell and tcl scripting
• Hands on experience in tape-out of at least three chips with at least one in 40/28 nm technology
• Work effectively in a multi-site, multi-cultural environment
• Self-motivated team player with strong organizational, time management and communication skills.


Job Functions:-
• Integration of various high speed mixed-signal IP components and digital control components into a synthesizable RTL
• In-depth understanding of the ASIC design flow to tapeout including all aspects of Synthesis, Auto Placement and Routing, DFT Scan implementation, Clock Tree implementation, Static Timing Analysis, Logic Equivalence Checking, DRC, LVS, DFM, parasitic extraction flows
• Creation and management of partitions for soft macros including development of SDC
• Guiding and mentoring junior team members to ensure completion of projects deliverables.
• Work on design closure topics including timing, power, noise, and physical verification
• Candidate should have exposure to current nanometer CMOS process technology, ASIC design flow and design methodology challenges and configuration/data management.

Contact HR: Rambus Chip Technologies India Pvt Ltd

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