- Required Skills / Experience:- Education: BE/B.Tech /M.Tech from reputed colleges.
- Experience in ASIC tapeouts, preferably in 28nm, 45nm & 65nm, to leading foundries
- Experience in Block / Chip level P & R.
- Clear understanding and command over all aspects of physical design including technology, libraries, floorplan, timing, signal integrity and power dissipation.
- Skill and efficiency in scripting using Tcl or perl desirable
- Demonstrated ability to work in a team environment
- Tools - Synopsys ICC, Astro, PTSI, Calibre/Hercules DRC/LVS Responsibilities
- Implementation of multimillion gate ASIC designs in cutting edge process technologies (28nm, 45nm, 65nm, 90nm)
- Ownership of all aspects of physical design including floorplanning, place and route, clock distribution, parasitic extraction, timing closure, power and signal integrity analysis, DFM, and DRC/LVS sign-off. Meeting highly challenging schedule, performance, and quality constraints
Company Profile
Marvell India Pvt. Ltd
http://www.marvell.com
MARVELL – a Santa Clara based leading fabless semiconductor company with expertise in microprocessor architecture and digital signal processing, storage solutions, mobile & wireless MARVELL – a Santa Clara based leading fabless semiconductor company with expertise in microprocessor architecture and digital signal processing, storage solutions, mobile & wireless technology, networking and consumer products. With an outstanding history of delivering next generation products that are revolutionizing the way the world works.
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